1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device realizing reduction in size of a MOSFET for battery management which can be physically included within a secondary battery.
2. Description of the Related Art
As portable terminals have become widespread, small high-capacity lithium ion batteries have been required. A protection circuit board for battery management of the charge/discharge of a lithium ion battery should be smaller and sufficiently resistant to load short circuit because of the need for weight reduction of the mobile terminals. Such a protection circuit device is required to be smaller since the protection circuit device is placed within a container of the lithium ion battery. Such a demand for a smaller protection circuit device has been fulfilled by using a Chip on Board (COB) technology which uses many chip parts. On the other hand, however, since a switching element is connected to the lithium ion battery in series, on-resistance of the switching element needs to be also reduced to an extreme degree. This is essential for increasing talk time and standby time in mobile phones.
FIG. 5 shows a specific protection circuit performing battery management. Two power MOSFETs Q1 and Q2 are connected to a lithium ion battery LiB in series. The two power MOSFETs Q1 and Q2 are on/off controlled while the voltage of the lithium ion battery LiB is detected by a control IC so that the lithium ion battery LiB is protected from over-charge, over-discharge, and load short circuit. In the two power MOSFETs Q1 and Q2, drain electrodes D are connected in common, and source electrodes S are located in both ends of the power MOSFETs Q1 and Q2. Gate electrodes G thereof are individually connected to the control IC.
In each of these power MOSFETs Q1 and Q2, a bidirectional zener diode for protection is connected between the gate and source electrodes in order to protect a thin gate oxidation film from electrostatic discharge damage.
In charging, both ends of the lithium ion battery LiB are connected to a power supply, and charge current is supplied to the lithium ion battery LiB in a solid-arrow direction in the drawing for charging. When the lithium ion battery LiB is over-charged, the control IC detects the voltage of the lithium ion battery LiB and changes the gate voltage of the power MOSFET Q2 from H (High level) to L (Low level). The power MOSFET Q2 is thereby turned off and breaks the circuit to protect the lithium ion battery LiB.
In discharging, both ends of the lithium ion battery LiB are connected to a load, and the lithium ion battery LiB drives a mobile terminal until the voltage of the lithium ion battery LiB falls to a predetermined voltage. When the lithium ion battery LiB is over-discharged, the control IC detects the voltage of the lithium ion battery LiB and changes the gate voltage of the power MOSFET Q1 from H to L. The power MOSFET Q1 is thereby turned off and breaks the circuit to protect the lithium ion battery LiB.
Furthermore, when a load short circuit occurs or when an overcurrent flows, a large current flows through the power MOSFETs Q1 and Q2, and voltage between both ends of the power MOSFETs Q1 and Q2 rapidly increases. Therefore, the control IC detects this voltage and, similarly to the case of discharging, turns off the power MOSFET Q1 to break the circuit, thus protecting the lithium ion battery LiB. However, a large current flows during a short period of time before the protection circuit works. Therefore, the peak drain currents of the power MOSFETs Q1 and Q2 are required to be large.
For such battery management, there is an increasing demand for a so-called one-chip dual MOSFET in which two MOSFETs are integrated into a single chip with drain electrodes of both the MOSFETs shared.
FIG. 6 shows an example of a conventional one-chip dual MOSFET. A one-chip dual MOSFET 33, obtained by integrating two power MOSFETs 33a and 33b into a single chip, includes source electrodes 41 and gate pad electrodes 42 on a surface thereof. In an entire back surface thereof, metal is deposited to serve as a common drain electrode (not shown) shared by the two power MOSFETs 33a and 33b. The power MOSFETs 33a and 33b are symmetrically arranged with respect to a center line X—X of the chip. The gate pad electrodes 42 of the power MOSFETS 33a and 33b are independently arranged in corners of the chip. A large number of MOSFET cells are arranged under the source electrodes 41.
FIGS. 7A and 7B show the aforementioned power MOSFET mounted on a lead frame. FIG. 7A is a top view, and FIG. 7B is a sectional view taken along a line D—D in FIG. 7A.
A lead frame 37 is a stamped frame made of copper. The power MOSFET 33 is fixed on a header 37h of the lead frame 37 with a preform material made of solder or Ag paste. The drain electrode is formed of a gold backing electrode (not shown) on a lower surface of the power MOSFET 33, and the gate pad electrodes 42 and the source electrodes 41 are formed on an upper surface of the power MOSFET 33 by sputtering an aluminum alloy. Further on an upper side of this power MOSFET 33, a metal multilayer film of Au or the like is deposited in order to reduce contact resistance with solder and a conductive material. The drain electrode of the MOSFET is fixed to the header 37h of the lead frame, and the header 37h is connected to drain terminals 37d. The gate electrodes are connected to gate terminals 37g through the gate pad electrodes 42 by bonding wires 34, and the source electrodes 41 are electrically connected to source terminals 37s by bonding wires 34.
The MOSFET 33 and the lead frame 37 are sealed with resin by transfer molding using a mold, and a resin layer 38 forms a package outline. The frame is mounted on a printed circuit board by solder or the like.
Note that the drain electrode is led out as the drain terminal 37d in FIGS. 7A and 7B, but in the case of the dual MOSFET employed in the protection circuit shown in FIG. 5, only four terminals, the source terminals 37s and the gate terminals 37g, of the chips are used.
In addition, the MOSFET may be mounted in a package in a flip-chip fashion, in which solder bumps 35 are provided to be individually connected to the source and gate electrodes on the surface, and the source and gate electrodes are electrically connected to external terminals 37 through the solder bumps 35 (for example, see Japanese Patent Laid Open Publication No. 2002-368219).
As described above, a MOSFET employed for protecting, for example, a lithium ion battery is a four-terminal element which includes two chips (MOSFET) with the drain electrodes thereof short-circuited and with the source and gate electrodes thereof led to the outside.
In such a case, a dual MOSFET is generally employed which is a single chip obtained by integrating two MOSFETs. However, the dual MOSFET requires twice the area of one MOSFET since the two chips are arranged side by side to form the single chip, resulting in a mounting area being increased.
Moreover, in the wire bonding type shown in FIGS. 7A and 7B, the on-resistance cannot be reduced since the resistance of the bonding wires is large. On the contrary, the flip-chip type uses solder bumps as connection means instead of the bonding wires, so the resistance of the connection means can be reduced compared to that of the wire bonding type. However, although current between both chips flows through a frame portion having a lower resistance (R1) than that of the substrate, in the wire bonding type, the current flows through the substrate in the flip-chip mounting type. Therefore, resistance R2 between the drain electrodes is disadvantageously increased. Accordingly, even this flip-chip mounting method has a limit of reduction in on-resistance.
In addition, as for the flip-chip type, there is a method of reducing the resistance between the drain electrodes by fixing a metal plate on the back surface of the chip. However, according to this method, the flip-chip dual-MOSFET requires a mounting area twice the size of a single chip, leading to a problem of little progress in size reduction.